Design And Development Of An FPGA Based DDFS Signal Generator
Muteithia, Walter Maina
MetadataShow full item record
Over time there has been an increase in speed and density of Field Programmable Gate Arrays (FPGAs), this has enabled more complex designs to be constructed within a short time frame. In addition, the flexibility of FPGA devices has also eased the integration of a design with a wide variety of components on a single chip. The aim of this study was to design and implement an FPGA based direct digital frequency synthesizer (DDFS) signal generator. The focus was on spectral purity improvement. Since phase and amplitude samples in a DDFS are represented using a finite word length, the output signal of a DDFS is usually faced by a spectral purity challenge. The details of this challenge and how to deal with it is also covered in this thesis. The design flow used in this work entailed modeling and simulation at the software level using SystemC and prototyping in hardware using Actel’s fusion field programmable gate array (FPGA). The resulting FPGA prototype had spurious free dynamic range (SFDR) improved from 48 dBc to 85 dBc and a noise floor of -116 dBc. Four signal types could be generated: sine, square, saw tooth and triangle. The frequency resolution was 0.047 Hz and the maximum output frequency was 25 MHz. Therefore, due to its high frequency resolution and spectral purity the proposed signal generator design can be useful in performing a wide range of laboratory experiments.